1. Technical Field
The present invention generally relates to buses, and more particularly, to buses that use varying voltage levels to communicate with various devices.
2. Related Art
Today's complex circuits and systems are often required to communicate with multiple devices during any given moment in time. This communication has typically been handled using a group of wires often referred to as a bus. There are various schemes for using a bus for communication of data, but nearly all of them involve assigning a unique address/identification to each device, an arbiter, and a master.
In general, the arbiter is responsible for receiving all the requests to use the bus, and determining which request to allow to proceed first (master). The addresses are used to determine which of the devices should receive the data currently being transmitted on the bus. The amount of time required to request permission for control over the bus from the arbiter (request cycle) can consume a significant amount of cycle bandwidth, particularly when multiple devices residing on the bus require the same data.
The significance of the overhead for such a request cycle is most notable in clusters of processors having their own submemory. Each of these clusters will often have common copies of code. Over time, the operating system will need to initialize/update these common sections of code, and the overhead of stepping through the clusters for this update can be a bottleneck for overall system performance.
It would, therefore, be a distinct advantage to have a bus protocol capable of transmitting the same data to multiple devices without the overhead of the request cycle scheme described above. The present invention provides such a bus protocol.